This invention relates generally to processing integrated circuits and more particularly to auto alignment marks used to align layer placement during processing of wafers.
When processing wafers, targets are placed to assure each layer is properly aligned with respect to prior layers. Within the targets, alignment marks are placed. Layers placed subsequent to the alignment marks, utilize the alignment marks for proper placement. The subsequent layer can then be aligned to the mark within an alignment error. The alignment error results from the error tolerances of the processing devices. See for example, Canon Reticle Alignment for Canon I-2000/I-2500 Stepper Model, available from Canon U.S.A. having a business address of 2051 Mission College Blvd., Santa Clara, Calif. 95054.
For example, in a first layer, master marks may be placed in each target. Subsequent layers are all aligned to these first layer master marks. This assures that every layer subsequent to the first layer will be aligned to the first layer within the alignment error. However, one problem with such a master mark alignment system is that the total alignment errors between layers other than the first layer is the square root of two times the alignment error. Thus immediately adjacent layers may be misaligned an amount up to the square root of two times the alignment error. In some processes this amount of error between adjacent layers may be excessive.
Alternately, each layer may include alignment marks for each target. Each layer is aligned using alignment marks composed of material from the immediately prior layer. This guarantees that immediately adjacent layers are misaligned at most an amount equal to the alignment error. However, use of such a sequential mark alignment system may result in a "walking error" wherein misalignment between layers which are not immediately adjacent to one another can be significantly larger than the alignment error.